Read JBL AUTHENTICS L8 (serv.man7) Service Manual online
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HARMAN INTERNATIONAL
Harman Consumer Group
Shenzhen,Guangdong,China
SIZE
TITLE
REV.
SHEET
OF
SCALE:
C
DRAWING NO.
ENG
CHECKED
DATE
CAD FILE:
B
REVISION HISTORY
REV
ECO
CHECKED
DATE
THOSE SPECIFICALLY AUTHORIZED IN WRITING BY HARMAN INTERNATIONAL
OR DISCLOSED TO OTHERS FOR MANUFACTURE OR ANY OTHER PURPOSE EXCEPT
CONTAINED THEREIN ARE PROPRIETARY AND ARE NOT TO BE REPRODUCED
PROPRIETARY INFORMATION - THESE DOCUMENTS AND THE INFORMATION
Cannot open file M:\02
Department\19
HCG_Engineering\Service\PC
B\Design_Template\Sch
template
(Altium)\untitled.bmp
Department\19
HCG_Engineering\Service\PC
B\Design_Template\Sch
template
(Altium)\untitled.bmp
1
2
L1
BLM18BD471SN1
C14
10NF
C15
10UF
GND
SPI_DSP_CS_FLASH
SPI_DSP_MISO_FLASH
SPI_DSP_MISO_FLASH
SPI_DSP_MOSI_FLASH
SPI_DSP_CLK_FLASH
+3V3_FLASH
+
C12
47UF
47UF
C13
100NF
100NF
+3V3_FLASH
Serial FLASH
(30mA)
3V3_VDDEXT
+3V3_VDDEXT
1
3
Y1
24.576 MHZ
C1
18PF
18PF
C2
18PF
18PF
GND
SPI_DSP_CS_FLASH
SPI_DSP_MISO_FLASH
SPI_DSP_MOSI_FLASH
SPI_DSP_CLK_FLASH
TP14
TP15
TP15
GND
nEMU
nTRST
TCK_ADSP
TMS_ADSP
TDI_ADSP
TDO_ADSP
nTRST
TCK_ADSP
TMS_ADSP
TDI_ADSP
TDO_ADSP
CLK_CFG0
CLK_CFG1
CLK_CFG1
MCU_nRESET_ADSP
SPDIF_in
GND
R68
10.0K
10.0K
JTAG
R
5
9
1
0
K
R
6
2
1
0
K
R
6
1
1
0
K
R
6
0
1
0
K
R
5
7
1
0
K
R
5
8
1
0
K
R49
100
R50
100
R51
33
R52
33
MCU_DSPWRACK
BOOT_CFG0
BOOT_CFG1
BOOT_CFG2
BOOT_CFG1
BOOT_CFG2
R23
0
R24
0
DAI_P1
76
DAI_P12
100
DAI_P11
103
DAI_P10
89
DAI_P13
74
DAI_P2
77
DAI_P3
55
DAI_P4
96
DAI_P5
87
DAI_P6
86
DAI_P7
73
DAI_P8
94
DAI_P9
88
DAI_P14
95
DAI_P15
101
DAI_P16
99
DAI_P17
98
DAI_P18
97
DAI_P19
75
DAI_P20
92
CLK_CFG0
22
BOOT_CFG0
7
BOOT_CFG1
14
BOOT_CFG2
106
CLK_CFG1
5
XTAL
25
RESET
173
DPI_P1
38
DPI_P2
39
DPI_P3
40
DPI_P4
43
DPI_P5
42
DPI_P6
44
DPI_P7
47
DPI_P8
46
DPI_P9
49
DPI_P10
50
DPI_P11
51
DPI_P12
52
DPI_P13
53
DPI_P14
54
FLAG1
135
FLAG0
134
FLAG2
136
FLAG3
138
TCK
164
EMU
146
TRST
144
TMS
174
TDI
158
TDO
151
GND5
145
GND1
137
GND2
139
GND4
142
RESETOUT/RUNRSTIN
36
CLKIN
24
GND3
140
THD_P
111
THD_M
110
U1B
ADSP-21489KSWZ-4B
To ADSP_24.576MHz
MCU_DSP_SPI_MOSI
MCU_DSP_SPI_MISO
MCU_DSP_SPI_CLK
MCU_DSP_SPI_CS
MCU_DSP_SPI_CLK
MCU_DSP_SPI_CS
DSP_WRITE
DSP_BUSY
DSP_BUSY
DSP_MCU_RX
DSP_MCU_TX
DSP_MCU_TX
R20
33
R39
33
R40
33
R22
1M
1M
DAI_reserve2
DAI_reserve1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CON2
CON_7X2 2.54MM
R41
33
R42
33
R43
33
R44
33
R45
33
R46
33
R47
100
R48
100
R53
100
R54
100
R55
0
R56
0
R21
10K
R
6
4
1
0
K
R
6
3
1
0
K
TP2
TP3
TP4
TP3
TP4
PVI_Reserve1
PVI_Reserve2
PVI_Reserve2
R67
10K
10K
R66
10K
10K
R65
10K
10K
GND
3V3_VDDEXT
Airplay_I2S_BCLK_in
DAI_reserver5
Airplay_I2S_Data0_in
Airplay_I2S_LRCLK_in
Airplay_I2S_LRCLK_in
42528_I2S_DATA0_in
42528_I2S_LRCLK_in
42528_I2S_BCLK_in
42528_I2S_MCLK_in
DSP_I2S_Data3_out
DSP_I2S_Data2_out
DSP_I2S_Data1_out
DSP_I2S_Data1_out
DSP_I2S_Data0_out
DSP_I2S_LRCLK_out
DSP_I2S_BCLK_out
DAI_reserver6
DAI_reserve3
DAI_reserve4
Authentic ADSP Module board
LH
1
2
F
2013/12/12
MCU_DSPDOCMD
R1
68
R2
68
R3
33
R4
33
R5
68
R6
68
R7
33
R8
33
R9
68
R10
68
R11
0
R12
33
R13
33
R14
33
R15
33
R16
33
R17
33
R18
33
R19
68
TP1
MCU_DSPWRACK
DSP_MCU_TX
DSP_MCU_RX
DSP_BUSY
DSP_WRITE
MCU_DSP_SPI_CS
MCU_DSP_SPI_CLK
MCU_DSP_SPI_MISO
MCU_DSP_SPI_MOSI
PVI_Reserve1
PVI_Reserve2
DAI_reserve1
Airplay_I2S_BCLK_in
Airplay_I2S_Data0_in
SPDIF_in
DSP_I2S_Data3_out
DSP_I2S_Data2_out
DSP_I2S_Data1_out
DSP_I2S_Data0_out
DSP_I2S_LRCLK_out
DSP_I2S_BCLK_out
Board_Version_DET
42528_I2S_DATA0_in
42528_I2S_LRCLK_in
42528_I2S_BCLK_in
Airplay_I2S_LRCLK_in
MCU_nRESET_ADSP
+3V3_VDDEXT
3V3_STY
GND
DAI_reserve2
DAI_reserve3
DAI_reserve4
Interface with Main Board
MCU_DSPDOCMD
DAI_reserver5
42528_I2S_MCLK_in
DAI_reserver6
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
CON1
FCI 67996-150, 2x25PIN,2.54mm
TP12
R82
10K
GND
GND
R
2
9
1
0
K
R
3
1
1
0
K
R
3
3
1
0
K
R
3
0
1
0
k
R
3
2
1
0
K
R
3
4
1
0
K
R
2
5
1
0
K
R
2
7
1
0
K
R
2
6
1
0
K
R
2
8
1
0
k
C3
100NF
100NF
CLK_CFG0
CLK_CFG1
BOOT_CFG0
BOOT_CFG1
BOOT_CFG2
CLK_CFG1
BOOT_CFG0
BOOT_CFG1
BOOT_CFG2
MCU_nRESET_ADSP
CLK_CFG1-0
0 0
0 1
1 0
1 1
CCLK to CLKIN RATIO
8 : 1
32 : 1
16 : 1
Reserved
BOOT_CFG2-0
0 0 0
0 0 1
0 1 0
0 1 1
Booting-Mode
SPI_Slave_Boot
SPI_Master_Boot
8-bit Flash Boot
INT_ROM
R
3
8
1
0
K
GND
Board_Version_DET
Board _Ver_DET
Board
0
1
Falcom
Sigma 300
R
3
7
1
0
K
3V3_STY
R36
GND
3V3_VDDEXT
N
M
N
M
SW
1
3V3_VDDEXT
R
3
5
1
0
K
NM
XOUT
1
S0
2
S1
3
S2
4
VDD1
5
GND1
6
CLK1
7
CLK2
8
REFOUT
9
CLK3
10
CLK4
11
GND2
12
VDD2
13
S3
14
VDD3
15
XIN
16
U2
AK8133E
1
3
Y3
27MHZ
C4
18PF
18PF
C5
18PF
18PF
GND
C9
100NF
100NF
GND
C8
100NF
100NF
GND
R
7
8
R
8
0
1
0
0
K
S3
S2
S1
S0
GND
C11
100NF
100NF
GND
+
C6
47UF
47UF
C7
100NF
L56
BLM18HD601SN1
+3V3_OSC
+3V3_OSC
+3V3_OSC
S3
S0
S1
S2
S1
S2
R81
10 OHM
C10
100NF
To ADSP_24.576MHz
R
7
9
1
0
0
K
R
7
7
R
7
3
1
0
0
K
R
7
4
R
7
5
R
7
6
1
0
0
K
GND
GND
GND
R71
33
R72
33
R266
0
0
R70
1M
+3V3_VDDEXT
+3V3_OSC
(18mA)
Clock Generator
+3V3_VDDEXT
TP7
TP8
TP8
TP5
TP6
TP6
N
M
N
M
N
M
N
M
N
M
N
M
N
M
To Codec_24.576MHz
To Codec_24.576MHz
TP26
TP27
(DSP_I2S_MCLK_out)
(Airplay_I2S_MCLK_in)
C94
12PF
C95
12pF
GND
C
9
6
2
7
p
F
C
9
7
2
7
p
F
C
9
8
N
M
C
1
0
1
2
7
p
F
C
1
0
2
2
7
p
F
C
1
0
3
N
M
C
1
0
4
2
7
p
F
C
1
0
5
2
7
p
F
C
1
0
6
N
M
C
1
0
7
2
7
p
F
C
1
0
8
N
M
C
1
0
9
N
M
C
1
1
0
N
M
C
1
1
1
N
M
C
1
1
2
N
M
C
1
1
3
N
M
C
1
1
4
N
M
C
1
1
5
N
M
C
1
1
6
N
M
GND
C
1
1
7
N
M
C
1
1
8
N
M
C
1
1
9
N
M
GND
L11
1K @ 100MHz
L12
0R
L13
0R
L14
0R
L15
L16
L17
L18
L16
L17
L18
L19
0R
L20
L21
L22
L23
L22
L23
SST25VF040B-80-4I-S2AF
CE#
1
SO
2
WP#
3
Vss
4
SI
5
SCK
6
HOLD#
7
VDD
8
U3
R112
NM
(DSP_I2S_MCLK_out)
(Airplay_I2S_MCLK_in)
R
1
1
3
N
M
OPTION only
For Debug
Fo
r D
eb
ug
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