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REV. 0
AD1955
PIN FUNCTION DESCRIPTIONS
Pin No.
I/O
Mnemonic
Description
1
DVDD
Digital Power Supply Connected to Digital 5 V Supply
2
Input
LRCLK/EF_WCLK
Left/Right Clock Input for Input Data in PCM Mode
Word Clock in External Filter Mode
Word Clock in External Filter Mode
3
Input
BCLK/EF_BCLK
Bit Clock Input for Input Data in PCM Mode
Bit Clock Input in External Filter Mode
Bit Clock Input in External Filter Mode
4
Input
SDATA/EF_LDATA
MSB First, Twos Complement Serial Audio Data
Two Channel (left and right), 16-Bit to 24-Bit Data in PCM Mode
Left Channel Data in External Filter Mode
Two Channel (left and right), 16-Bit to 24-Bit Data in PCM Mode
Left Channel Data in External Filter Mode
5
Input
EF_RDATA
Not used in PCM Mode
Right channel data in External Filter Mode
Right channel data in External Filter Mode
6
I/O
DSD_SCLK
Serial Clock Input for DSD Data. This clock should be 64
44.1 kHz,
2.8224 MHz or 128
44.1 kHz, 5.6448 MHz in Normal Mode, 128
44.1 kHz, 5.6448 MHz or 256
44.1 kHz, 11.2896 MHz in Phase Mode.
7
Input
DSD_LDATA
DSD Left Channel Data Input
8
Input
DSD_RDATA
DSD Right Channel Data Input
9
I/O
DSD_PHASE
DSD Phase Reference Signal. This clock should be 64
44.1 kHz,
2.8224 MHz. If not used, this pin should be connected low.
10
AGND
Analog Ground
11
Output
IOUTR+
Right Channel Positive Analog Output
12
Output
IOUTR–
Right Channel Negative Analog Output
13
Output
FILTR
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10
voltage reference with parallel 10
µF and 0.1 µF capacitors to AGND.
14
IREF
Connection Point for External Bias Resistor
15
AVDD
Analog Power Supply Connected to Analog 5 V Supply
16
Output
FILTB
Filter Capacitor Connection with Parallel 10
µF and 0.1 µF Capacitors to AGND
17
Output
IOUTL–
Left Channel Negative Analog Output
18
Output
IOUTL+
Left Channel Positive Analog Output
19
AGND
Analog Ground
20
Output
ZEROR
Right Channel Zero Flag Output. This pin goes high when the right channel
has no signal input or the DSD mute pattern is detected.
has no signal input or the DSD mute pattern is detected.
21
Output
ZEROL
Left Channel Zero Flag Output. This pin goes high when the left channel has
no signal input or the DSD mute pattern is detected.
no signal input or the DSD mute pattern is detected.
22
Input
MUTE
Mute. Assert high to mute both stereo analog outputs. Deassert low for nor-
mal operation.
mal operation.
23
Input
PD/RST
Power Down/Reset. The AD1955 is placed in a reset state and the digital
circuitry is powered down when this pin is held low. The AD1955 is reset on
the rising edge of this signal. The serial control port registers are reset to the
default values. Connect high for normal operation.
circuitry is powered down when this pin is held low. The AD1955 is reset on
the rising edge of this signal. The serial control port registers are reset to the
default values. Connect high for normal operation.
24
Input
CDATA
Serial Control Input, MSB First, Containing 16 Bits of Unsigned Data. Used
for specifying control information and channel-specific attenuation.
for specifying control information and channel-specific attenuation.
25
Input
CLATCH
Latch Input for Control Data
26
Input
CCLK
Clock Input for Control Data. Control input data must be valid on the rising
edge of CCLK. CCLK may be continuous or gated.
edge of CCLK. CCLK may be continuous or gated.
27
Input
MCLK
Master Clock Input. Connect to an external clock source.
28
DGND
Digital Ground
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