AVR 171 (serv.man3) - Harman Kardon Audio Service Manual (repair manual). Page 94

 

Data Sheet: DM Series 

DM860A Networked Media Processor 

 

dat_DM860A_1_1_datasheet.doc  

 

CONFIDENTIAL 

 

 

    

Version 1.1 – July 11

th

 2011 - Page 22 of 70 

 

                           

        

 

SSMD[7:0] 

D12, C12, B12, 
A12, D11, C11, 
B11, A11 

I/O Data 

lines 

SSMCLK C10 

O 

Clock 

output 

SSMCMD A13 

O 

Command 

output 

SSMCP 

D10 

I 

Card power input (high = off) 

SSMWP 

D9 

I 

Write protect input (low = protect) 

 

VCO[1:0] J2, 

K2 I 

External oscillator inputs, typically coming from an external VCO. 
Together with the external loop-filter and the internal clock dividers, 
each PDOUT/VCO pair can form a complete PLL. 

PDOUT[1:0] J1, 

K1  O Phase discriminator outputs. These signals are charge-pump type 

outputs. Each of them can be used to feed the loop-filter of a PLL 
structure. 

 

NRESET D13 

I 

Reset (active low). When asserted, the chip is placed in the 
reset state and the peripheral pins are configured as inputs. 
After deassertion of NRESET, the chip is clocked by XTALI and 
starts booting from the port configured by the FCLE, FALE pins. 
The NRESET signal must be asserted after power-up. 

XTALI K3 

I 

Oscillator circuit input. Internal system clock will be derived 
from XTALI (internal clock multiplier) 

XTALO J3 

O 

Oscillator 

circuit 

output 

RREF 

C7 

I 

Reference current. Connect a 3.0 kOhm ±1% resistor to GND. 

TEST1 

B10 

I 

Reserved. Connect to VDD for normal operation. 

HIGHZ 

A10 

I 

Reserved. Connect to VDD for normal operation. 

n.c. 

E4, F4, G4, 
H4, J4, V1, 
A4, A5, B4, 
B5, C8, C9 

– 

Pins must be left unconnected (18x) 

 

Harman Kardon

AVR 171 Service Manual

Page 94 of 174