AVR 151S (serv.man3) - Harman Kardon Audio Service Manual (repair manual). Page 100

6/34

These I

2

C-compatible electrically erasable programmable memory (EEPROM) devices are 

organized as 8192 × 8 bits (M24C64-x) and 4096 × 8 bits (M24C32-x).

I

2

C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. 

The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the 
I

2

C bus definition.

The device behaves as a slave in the I

2

C protocol, with all memory operations synchronized 

by the serial clock. Read and Write operations are initiated by a Start condition, generated 
by the bus master. The Start condition is followed by a Device Select Code and Read/Write
bit (RW) (as described in 

), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9

th

 bit 

time, following the bus master’s 8-bit transmission. When data is read by the bus master, the 
bus master acknowledges the receipt of the data byte in the same way. Data transfers are 
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

         

E0, E1, E2

Chip Enable

SDA

Serial Data

SCL

Serial Clock

WC

Write Control

V

CC

Supply Voltage

V

SS

Ground

AI01844c

3

E0-E2

SDA

VCC

M24C64-W

M24C64-R

M24C64-F

M24C32-W

M24C32-R

M24C32-F

WC

SCL

VSS

Harman Kardon

Page 100 of 131