Read Panasonic KX-NCP1170XJ (serv.man2) Service Manual online
11
KX-NCP1170XJ
• Power failure switching relays
Switching relays RL50A and RL51A are on board in order that one lines out of four can be directly connected to the outside line
in case of power failure. They will be directly connected to the line that is connected with the outside-line card connected by CN2
on the front of the board and 4-conductor TEL cord. In normal operation, the switching relays are in 'make' state. In case of
power supply down, they will be in 'break' state, and the power-failure direct-dial mode will be established.
in case of power failure. They will be directly connected to the line that is connected with the outside-line card connected by CN2
on the front of the board and 4-conductor TEL cord. In normal operation, the switching relays are in 'make' state. In case of
power supply down, they will be in 'break' state, and the power-failure direct-dial mode will be established.
• Bell signal issuing circuit
When feeding and speech paths are connected, BELL relay will be in 'break' state. When the bell signal is issued, BELL relay will
be in “Make” state.
be in “Make” state.
• HOOK detecting circuit
When BELL signal is not output or when dial pulse is received, this circuit distinguishes whether SLT is off hook or on hook.
When SLT is off hook, DC loop is formed and current flows into U52. At this time, the collector of U52 (3, 4, and 5 pin), namely,
HOOK signal changes from H to L and is detected by CPU by way of CODEC R ASIC. When SLT is on hook, DC loop is
interrupted and the current flow into U52 (3, 4, and 5 pin) ceases; the collector of U52, namely, HOOK signal changes from L to
H and is detected by CPU in like manner.
When SLT is off hook, DC loop is formed and current flows into U52. At this time, the collector of U52 (3, 4, and 5 pin), namely,
HOOK signal changes from H to L and is detected by CPU by way of CODEC R ASIC. When SLT is on hook, DC loop is
interrupted and the current flow into U52 (3, 4, and 5 pin) ceases; the collector of U52, namely, HOOK signal changes from L to
H and is detected by CPU in like manner.
• Ring trip circuit
While BELL signal is output, this circuit detects SLT off-hook by the hardware, and makes BELL relay in 'break' state.
While BELL signal is issued, when SLT is on hook, U52 (1, 2, and 6 pin) is off. When SLT is taken off the hook, DC loop is
formed because 40V is superimposed on BELL signal; then, current flows into R52
While BELL signal is issued, when SLT is on hook, U52 (1, 2, and 6 pin) is off. When SLT is taken off the hook, DC loop is
formed because 40V is superimposed on BELL signal; then, current flows into R52
→ R58 → D51 → U52, and U52 (1, 2, and 6
pin) becomes on.
When U52 (1, 2, and 6 pin) has become on, because the base of Q57 that is the driver of BELL relay becomes L, BELL relay will
be in 'break' state and SLT current-supply circuit feeds current to SLT.
When U52 (1, 2, and 6 pin) has become on, because the base of Q57 that is the driver of BELL relay becomes L, BELL relay will
be in 'break' state and SLT current-supply circuit feeds current to SLT.
• DTMF signal detecting circuit
Each port has its DTMF receiver.
Ports A to D carry out detection at IC400.
That DTMF data has become valid at EST terminal = H is detected by CPU by way of CODEC
Ports A to D carry out detection at IC400.
That DTMF data has become valid at EST terminal = H is detected by CPU by way of CODEC
→ ASIC, and then CPU reads and
detects the data of DTMF receiver.
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